The present study is a continuation of the results published in previous publications of the authors, which are used here. In the light of the widespread negative attitude towards the phenomenon of metastability in logic circuits, leading to their frequent erroneous switching, the study substantiated one benefit of this phenomenon. Based on the analysis and manifested useness of metastability, it was found that there are certain problems in the organization of the functioning of computer structures, which can be solved by successful using of this phenomenon. As a result, a definition for the logical operation of asynchronous arbitration is formulated. Based on its logical synthesis and hardware implementation, a two-input asynchronous arbiter is synthesized. Then, two possible logic circuits are presented, which are realized possibilities for operation control. The statement that the synthesized arbiter is as sensitive and fast as possible is substantiated. A definition for arbitration operation is introduced and a logic function is synthesized for each output of the multi-input asynchronous arbiter. This created a methodology for the synthesis of fast combined asynchronous multi-input arbiters. The quantity of the basic hardware units when designing an n-input combined asynchronous arbiter is estimated. Both qualitative and quantitative assessments are given. The analysis of the final latencies of the events is performed and a logical structure for their measurement is proposed.

CCS CONCEPT• Hardware • Integrated circuits • Logic circuits • Asynchronous circuits. 

Additional Keywords and Phrases:  Asynchronous arbitration, Multi-input arbiter, Latency.   Fast Asynchronous Arbiters.

      Operation division is the slowest of the four basic arithmetic operations performed in arithmetic-logic devices. In this paper we offer a proposal to speed up computations based on non-restoring division algorithm by the use of the radix-2 two's complement signed numbers. Fast computation is achieved by the early termination of the algorithm when the relevant condition is in place. A hardware implementation of the solution is proposed.

       http://dl.acm.org/citation.cfm?id=3274009 

      The logical synthesis of an asynchronous micro-pipeline controller for a micro-pipeline unit with conditional algorithmic branch is presented. The condition for branch is generated by the operation comparison. The comparison by a digital comparator enables the realization of a unique 3-alternative conditional branch. Such a branch can’t be software implemented. Only the hardware realization of the operation comparison generates such a unique conditional transition. The synthesized logical circuits of the logical units in the structure of the micro-pipeline controller are presented. The digital comparator as a part of the micro-pipeline unit generates transition flags LT, EQ and GT, defining each of the conditional transitions only into direction “true” (logical “1”). It is shown that the implementation of other conditions for a transition is basically possible by additional hardware resources that do not change the concept of the pipeline controller. The synthesized pipeline controller implements 2-phase transfer protocol. Key words: Asynchronous Micro-Pipeline, Nonlinear Pipeline, C-element, Pipeline Controller.

    http://dl.acm.org/citation.cfm?id=2983503&CFID=697072631&CFTOKEN=36879544

      A thorough and detailed analysis of anasynchronous 4-phase transfer protocol with early-zero reset is presented. The protocol is implemented by a micro-pipeline controller whose register-fixative (pipeline register) is implemented by dynamic (Edge) flip-flops, writing data by the rising edge of the signal. Based on this analysis two original results are obtained. The first one: the possible time interval for the reset of the micro-pipeline controller is defined. The second one is about the possibility of false switching of the controller. Different variants of logic schemes are commented in relations with the findings of the analysis. Technical requirements which the logical synthesis is based on are defined for both problems. The principle logical circuit of the pipeline controller is presented. It’s functioning is explained in details by a timing diagram.

    http://dl.acm.org/citation.cfm?id=2812428.2812452&coll=DL&dl=GUIDE

http://www.scitechnol.com/completion-detection-model-for-a-digital-comparator-vt7j.php?article_id=3260  

http://www.scitechnol.com/logic-scheme-for-determining-the-number-of-leftmost-insignificant-digits-in-a-bitset-of-any-length-hRjK.php?article_id=3259   

 http://scitechnol.com/multiform-multiformat-digital-comparator-TlBS.php?article_id=1979  

      Main focus of this article is the performance estimation of any arbitrary computational structure in various forms of control organization. Four organization cases are observed – sequential processing of high number of tasks by classical control of the computing structure using (synchronous and asynchronous) end state machine and parallel processing of tasks, organized in pipelined computational structure (synchronous and asynchronous controlled). The latency of each operational level is approximated with normally distributed random variable.

    http://www.academicpublishingplatforms.com/article.php?journal=ATI&number=7&article=1628  

       High latency micro-pipeline stage problem is analyzed. It is shown that in order to achieve steady pace into pipeline is necessary to apply superscalar approach. The formula for machine duplication degree is defined. The problems derived from this type of machine parallelism are stated. Synthesis of the micro-pipeline automat at the branch dot is presented in two variants – for 2-phase and 4-phase transfer protocol.

    http://www.academicpublishingplatforms.com/article.php?journal=ATI&number=6&article=869  

       This paper considers problems related to hardware implementation of computational process with conditional jumps. Hardware refers to asynchronous pipeline organization at microoperational level. Exploration is dedicated to one of the tasks presented in (Tyanev, D., 2009) concerning to micropipeline controller design to control micropipeline stage into joint dot of branch algorithm. Joint dot is the point at which few preceding branches are combined. It appears inevitably into conditional jump structures and this is the reason for the actuality of its problem. Analysis of this new task is presented and request arbitration functioning principles are formulated for the incoming to joint dot requests. The arbiter is responsible for the fair choice on which depends steady peformance of separate pipeline brances. Paper also describes pipeline controller synthesis and analysis of its operation in two variants: about 2-phase and 4-phase data transfer protocol. The synthesized asynchronous arbiter scheme is invariant to the type of pipeline protocol.

     http://www.academicpublishingplatforms.com/article.php?journal=ATI&number=5&article=743  

       The paper considers structural problems in synthesis of micro-pipelines which implement algorithms with conditional jumps. These structures require pre-definition of the term "micro-pipeline". As a result there are defined, analyzed and described four new scientific tasks necessary for solving this common problem. The paper presents the solution of only one of the tasks -- synthesis of micro-pipeline that controls section generating value of the transition condition, as well as the connection of this section with initial stage controllers into both branches. The complete logical synthesis is explained and as a result logical structures of pipeline controllers are obtained in two variants: for 2-phase data transfer protocol and for 4-phase data transfer protocol.

       The paper focuses on the problem of hardware implementation of computational process containing conditional transitions. Asynchronous organization of pipelines at microoperational level is provided for the hardware. Its characteristic feature is that it includes both one and multi-cycle micropipeline units. Because of these circumstances, the outgoing pipeline results do not correspond in the same order to the tasks running in the pipeline. The article presents the synthesized original logical structure of the micropipeline buffer and a specific to its service strategy through which their correct order is restored when reading results from the buffer. Another programming model of the structure of the buffer is described, by which its behavior was studied in different possible situations. In addition, a programming model of the structure of the buffer was created and its behavior in different possible situations is examined. The results of numerical experiments with the programming model are presented. Based on them recommendations are formulated about the parameters of the buffer and the structure of the pipeline.

     http://www.academicpublishingplatforms.com/article.php?journal=ATI&number=4&article=426  

       A new design is presented, which manages the problem with the internal race conditions in two types of micro-pipeline units (stages), which on their turn are hardware implementations of count-controlled loops. The, implemented in the new design synchronization, eliminates the typical for the structures limitations and makes their operability fully synchronous and highly reliable.

       A micro-pipeline, which consists of one-cycle and multi-cycle micro-pipeline units, is considered. Along with the purpose to design unified and independent of the micro-pipeline unit structure control circuit, a unified interpretation of the pipeline organization is proposed. This interpretation sets to foreground the write to pipeline register micro-operation. The implementation of a pipeline according to that interpretation is limited by the type of the registers, used to store the pipeline stage data, which are registers using only one edge (rising or falling). The mentioned limitation necessitates the usage of four-phase pipeline unit communication protocols. Accordingly, an asynchronous micro-pipeline and its control are designed. The control is capable of combining the two types of micro-pipeline units. The operation of the protocol is shown.

       The interface of multi-stage micro-pipeline sections building continuous micro-pipelines is defined and analyzed. As the multi-stage micro-pipeline sections have own memory, such micro-pipelines don’t need additional registers. In these conditions there is pipeline asynchronous protocol and implementing control unit synthesized. The protocol’s operation is shown in cases, arising from combined work of neighbor multi-stage micro-pipeline sections. Possible problems of combining one- and multi-stage sections are indicated.

Document_V_53_ENG.pdf 122.24 KB  

       In the present work, an original logic structure of control unit based on finite state machine, with hardwired rules (FSMHRCU), working with floating cycles duration is presented. The structure may be used as basis for the implementation of either Mealy or Moore finite state machine. The operation of the synthesized structure is clarified schematically and graphically. The possibility of the execution of nano- and pico-programs in the terms of the current micro-command from the sequence of micro-commands of the controlling algorithm, is presented. The structure supplies aperiodicity in these low levels and it is synthesized and presented below in the paper.

Document_V_50_ENG.pdf 296.27 KB

       This paper presents a novel methodology for design of operational computational devices, realizing a diversity of condition-controlled loop algorithmic structures. The synthesis of such a structure takes in count just the necessary for the computation signal changes, which makes the synthesis of controlling finite state machine unnecessary. Thus the resulting controlling circuit is tightly coupled with the logic one. In this sense the structure can be defined as self-controlling and can be part of micro-pipeline structure with certain delay. The structures in either case are as fast as possible. Experiments have been made with Xilinx’ FPGA chip.  

       This paper presents a novel methodology for design of operational computational devices, realizing a diversity of condition-controlled loop algorithmic structures. The synthesis of such a structure takes in count just the necessary for the computation signal changes, which makes the synthesis of controlling finite state machine unnecessary. Thus the resulting controlling circuit is tightly coupled with the logic one. In this sense the structure can be defined as self-controlling and can be part of micro-pipeline structure with certain delay. The methodology can be applied when designing either synchronous or asynchronous structures. The structures in either case are as fast as possible because they can be organized in pipeline fashion.  

       This article explores two original hardware solutions for service of queues. The three-clock cycle is proven as a necessity for a reliable choice process. Two logic structures are presented: one-clock and many-clock, each capable of servicing the two types of queues - with and without jumping. The algorithms representing the structures' functioning are thoroughly explained. The schemes allow a wide degree of adaptivity and can easily be integrated into projects, based on FPGA or CPLD, when constructing interrupt control systems, arbitrary systems, etc. 

       The present research represents a novel method for operational structures design, which implement a versatile set of count-controlled loop algorithms. Main feature of these structures is that they operate without controlling automata. The method can be used for the design of synchronous and asynchronous structures. It simplifies the structures, gives us the ability to organize the structures in pipeline fashion, which results in better throughput.

  Document_V_45.pdf  463.19 KB

       This article consider/explore simultaneously addition of more than two integer numbers problem through (3:1) concentrators. Presented results are extension of previously published research of the problem, solved about horizontal organized addition. In this paper we discuss second possible organization, referred as vertical addition. Logical structure, which implements such organization, has been synthesized and analyzed. The analysis, as well as obtained quantitative estimations of machine costs and switching time, is presented. Conclusions based on the comparison of the two structures were made. Recommendations for design of solutions with different parameters have been formulated. Particular examples have been molded and implemented experimentally through Xilinx tools.

  Document_V_43_ENG.pdf  249.97 KB

       The new approach was explored for hardware implementation of calculation procedure, the cardinal characteristic to which the rule of the synthesized procedure structures in the absence of microprogram control in the synthesized operational structures. The general method for the hardware execution is exposed in the present work on autonomous loop algorithmic structures. The operating capability to the represented structures is showed by modeling and practical experiment in real calculation drives on the base of the company Xilinx.

  Document_V_42.pdf  347.75 KB

      This document presents a new method for design of operational computational devices, in a way that a FSM is removed from the design. The method can be used for the design of synchronous and asynchronous devices. The main advantages of the method are the simplification and homogenization of the devices and as well the opportunity of increasing the output of the computational devices.

  Document_V_41_ENG.pdf  187.93 KB

       This article consider/explore simultaneously addition of more than two integer numbers problem through (3:1) concentrators. Presented results are extension of previously published research of the problem, solved about horizontal organized addition. In this paper we discuss second possible organization, referred as vertical addition. Logical structure, which implements such organization, has been synthesized and analyzed. The analysis, as well as obtained quantitative estimations of machine costs and switching time, is presented. Conclusions based on the comparison of the two structures were made. Recommendations for design of solutions with different parameters have been formulated. Particular examples have been molded and implemented experimentally through Xilinx tools.

  Document_V_39.pdf  660.64 KB

         This paper submit the idea for parallel at time adding of more than two integer numbers with schemes, known as concentrators. A logic structure of adder with multiple inputs, based on three-input adder, is offered. Theorem for the highest length of the sum is proved in conditions of arbitrary numbers. On the ground of this theorem there are analytical estimations of implementation costs and switching time. Comparative analysis of the competitive schemes is shown. The conclusions proof acceptability of both researched idea and offered scheme. The experiments with the schemes were made with the help of Xilinx tools and FPGA-family Spartan II.

  Document_V_37_ENG.pdf  282.85 KB 

        In the present paper we made an analysis of different matching criteria, which are applied when a task of template matching is solving. It is made an analysis of the experimental results, which are derived when these different criteria are applied on the selected sets of representative points. Comparisons are made about two basic criteria – speed and how they cope with any type of distortions.

  Document_V_34_ENG.pdf  393.33 KB

        Many edge detectors are described in the literature about image processing, where the choice of input parameters are to be made by the users. In many cases such choices are made intuitively. In this paper we propose the choice of threshold to be based on the visual perception of the edge. Using our earlier edge definition and proposed algorithm for edge detection we formulate a mini-max rule for threshold determination. This rule uses the values of the second derivative of intensity function. Choice of the most significant values of second derivative allows to separate areas, which contain edges. The proposed approach is applied in the developed by the authors edge detector. The derived results are satisfactory.

Document_V_33_ENG.pdf  157.29 KB

      This research is devoted to the problems in the field of black and white image processing which are connected with the purpose to detect the maximum number of edges and to determine their coordinates as exactly as possible. It is made a critical analysis of the commonly accepted definition of the edge, modeled as a ramp. Consent to this definition there is only an edge, which position is in the middle of the ramp connecting low and high level of intensity. Here authors give a new edge definition; according to it there are two edges (contrary to the classical definition) – one on the low level and a second one – on the high level of intensity. As a result of this understanding, suggested here definition is mathematically formalized by the interrupted first derivative of the intensity function. Based on this definition authors work up an edge detector achieving sub-pixel accuracy when detects edge points’ coordinates. There are synthesized appropriate test images and some of the well known edge detectors and the here suggested one are applied to them. Results confirm authors’ expectations for accuracy of localization and high informativity in the description of the objects in black and white images, which comes very close to their visual susceptibility.    

      Template matching is one of the most important problems in the vision industry. This problem is solving by many different ways, but along with the requirements of high reliability, there are high requirements of run-time decreasing. One of the ways to speed-up the processing is to reduce the number of points (pixels) which take part in the calculations. We propose a new method for important point’s extraction, based on the equipotential surfaces. By the properly potential threshold these surfaces give a possibility to extract the elements of searched subset of points, which are in conformity with the criterion of D-optimality. The successful fulfillment of this extraction can be made by the properly conditions. For this purpose we propose a method for nonlinear interval transformation of the color function. This transformation leads to the image contrast improvement and thence to the more easily determination of the coordinates (x,y), corresponding to the intersected points of the relief with the surface of the properly chosen potential.  

       According to the analysis of the McLaren-Marsaglia’s method for random sequences generation is established the possibility that the function which services the temporary buffer to be interpreted as a hash-function. As a result of this conclusion a new function of multiplicative type is suggested. There are described the results of the modified algorithm compared to the original one, based on Kolmogorov’s criteria.

 Document_V_27_ENG.pdf  56.06 KB  

        As a criterion for assessment of computer generators of random numbers with standard normal distribution, a limit is offered, corresponding to an estimated level of risk. A method for calculation of the criterion is being proposed, as well as the results of its application.

      The objects of comment in this paper are the deficiencies of computer generated standard normal statistical samples yielding to the N(0,I) law and the impossibility of the generators to guarantee the statistical parameters assigned in advance. An approach for appropriation of the statistical samples of a priori known mean vector and covariance matrix in absolute conformity with the N^(k)(v,С) law is suggested.

 Document_V_26_ENG.pdf  172.87 KB  

      The object of discussion in this study are the foremost means for data input through the channels for direct memory access by ISA-based controllers, intended for synchronic and asynchronic analog-digital conversion. The requirements of the process of transfer needed for synthesis are also clarified. The potential technical and program solutions are based on two of the DMA-controller operation modes - single transfer mode and block transfer mode.

  Document_V_24_ENG.pdf 192.69 KB  

      On the basis of a critical analysis of the orthogonal transformations used in the problems of pattern recognition, a new method of approach is suggested, which is meant for the optimization of the orthogonal feature spaces. This approach consists in accomplishment of consecutive secondary orthogonal transformations by manipulating the parametres of the eigen basis systems to the optimal point of view. The latter is determined by the use of the term secondary scalar feature. In connection with the introduced presentation of classes, a classification rule is formulated.

  Document_V_25_ENG.pdf  167.97 KB  

       This paper presents harware and software realization of ADC-controller fot IBM compatible AT/PC; exchanging data via 16-bits chanels, by DMA. ADC converts two input signals parallel in time. Two additional pulse imputs of the controller mark the current reports in thr two channels. This makes the system convinient for control and analysis of fast - going processes in rotational or reciprocating drive objects, which require link between monitored processes and certain one. The software for the controller consists of two parts - basic and applicable one. Rezults from real use the hardware in control and analysis of the combustion processes in diesel engines are also presented.

       The paper deals with the problem of forming teaching sample from the statistics accumulated for given class. The teaching sample should guarantee a qualitative teaching of the identifying algorithm, more over a sertain level of its efficiency is achieved at less volume of the same. For this purpose the criterion of D-optimum of the sample is applied in cojunction with the method for SVD when computing the determinants. As a result, procedure for forming sample of given volume is syntesized. Estimates of quality of the linear dividing funkction are made when teaching the so formed teaching sample. The results from the computing experiment with linear dividing function teached in different ways for solving concrete problem of ship's diesei engine diagnostics are shown.

       The effect of various alterations in preload, afterload and inotropic state of the left ventricle on the derivative of the left apex cardiogram (dA/dt) was studied in anaesthezed dogs, in an attempt to clarify some of the determinants of the positive peak of dA/dt and time interval from the onset of ventricular contraction to the maximal dA/dt (t-peak dA/dt). The first derivative of the apex cardiogram was recorded simultaneously with left ventricular pressure, conventional left apex cardiogram, the first derivative of left ventricular pressure, electrocardiogram and phonocardiogram. Both dA/dt and dP/dt curves similar in contour and were found to occur nearly simultaneously. This close relation was preserved during various acute haemodynamic chages. Peak positive amplitude dA/dt was closely related to the myocardial inotropic background and to the pre- and afterload. In addition, t-peak dA/dt was inversely dependent on the ventricular inotropic state and statistically non-significant changes on varying the loadeng condition.
        It is concluded that the combination of peak positive amplitude dA/dt and t-peak dA/dt allow a more precise and complete estimation of changes in contraetility than could be obtained from peak amplitude dP/dt used separately.