Publications :: Publications
Tyanev D.S., Petkova Y.P., Angelov M.G. FAST ASYNCHRONOUS ARBITERS. DETERMINING FINAL DELAYS Proceeding of the 23rd International Conference CompSysTech’22, Ruse, Bulgaria, 1718 June 2022, pp.713.
The present study is a continuation of the results published in previous publications of the authors, which are used here. In the light of the widespread negative attitude towards the phenomenon of metastability in logic circuits, leading to their frequent erroneous switching, the study substantiated one benefit of this phenomenon. Based on the analysis and manifested useness of metastability, it was found that there are certain problems in the organization of the functioning of computer structures, which can be solved by successful using of this phenomenon. As a result, a definition for the logical operation of asynchronous arbitration is formulated. Based on its logical synthesis and hardware implementation, a twoinput asynchronous arbiter is synthesized. Then, two possible logic circuits are presented, which are realized possibilities for operation control. The statement that the synthesized arbiter is as sensitive and fast as possible is substantiated. A definition for arbitration operation is introduced and a logic function is synthesized for each output of the multiinput asynchronous arbiter. This created a methodology for the synthesis of fast combined asynchronous multiinput arbiters. The quantity of the basic hardware units when designing an ninput combined asynchronous arbiter is estimated. Both qualitative and quantitative assessments are given. The analysis of the final latencies of the events is performed and a logical structure for their measurement is proposed.
CCS CONCEPT• Hardware • Integrated circuits • Logic circuits • Asynchronous circuits.
Additional Keywords and Phrases: Asynchronous arbitration, Multiinput arbiter, Latency. Fast Asynchronous Arbiters.
Tyanev, D. S., Petkova, Y. P. MULTIINPUTS ASYNCHRONOUS ARBITER WITH PARALLEL CONNECTION OF INPUT SIGNALS. ARBITRATION IN CONDITIONS OF SUPERSCALARITY Proceeding of the International Conference CompSysTech’21, Ruse, Bulgaria, June 2021, pp 1822.
The research is devoted to problems caused by the impossibility to satisfy the requests for immediate service of a subscriber of a given resource in the conditions of various forms of parallelism. It is stated that the solution to the problem consists in abandoning a parallel organization and moving to a sequential one, which requires the introduction of a certain order of service, as well as equipment for its implementation. A new solution is presented, implementing an order of asynchronous arbitration based on the understanding of the competition of service requests over time. Based on this line, a system for synthesis of a multiinput asynchronous arbiter with parallel joining of input events is presented. The form of parallelism known as superscalarity is specifically considered. The study showed that arbitrage in the context of a superscalar resource is a new and unexplored task. Its decision requires arbitration of the second event in an order, and if necessary, subsequent ones in time.
CCS CONCEPT • Hardware • Integrated circuits • Logic circuits • Asynchronous circuits
Additional Keywords and Phrases: Asynchronous arbitration, Multiinput arbiter, Superscalarity
Tyanev, D. S., Petkova, Y. P. ASYNCHRONOUS ARBITRATION. SYNTHESIS OF MULTIINPUTS ASYNCHRONOUS ARBITER WITH CONSECUTIVE CONNECTION OF INPUT SIGNALS Proceeding of the International Conference CompSysTech’21, Ruse, Bulgaria, June 2021, pp 2327.
The research is devoted to problems caused by the impossibility to satisfy the requests for immediate service of a subscriber of a given resource in the conditions of various forms of parallelism. It is stated that the solution to the problem consists in the abandonment of a parallel organization and the transition to a consecutive one, which requires a certain order of service, as well as equipment for its implementation. A new solution is presented, which implements an order of asynchronous arbitration based on the understanding of the competition of service requests over time. Based on this, a specification for the synthesis of a metastable element and as a result of a fast twoinput arbiter is formulated. Based on the latter, a system for synthesis of a multiinput asynchronous arbiter with sequential joining of input events is presented.
CCS CONCEPT • Hardware • Integrated circuits • Logic circuits • Asynchronous circuits
Additional Keywords and Phrases: Asynchronous arbitration, Metastable element, Arbiter
Tyanev, D. S., Petkova, Y. P. ARITHMETIC OPERATION DIVISION. QUOTIENT AND REMAINDER. LOGICAL STRUCTURES AND CALCULATION SCHEMES Íàóêîâ³ ïðàö³ ÄîíÍÒÓ, Ñåð³ÿ “²íôîðìàòèêà, ê³áåðíåòèêà òà îá÷èñëþâàëüíà òåõí³êà”, ISSN 19961588, ¹1 (28)2 (29), 2019.
A project for fast execution of operation division on signed integer numbers is presented. The final result of the synthesis is a complete and unique combinational scheme. Synthesis requires a presentation of the theoretical ground for operation division and the resulting algorithms for calculating the quotient and the remainder. The operands and the results of the operation are twos’ complement numbers. The first part of the article presents the synthesis of the logical structure and of the combinational scheme for calculation of the first result  the quotient. The second part presents the synthesized algorithm and the logic scheme for calculating the second result  the remainder. The entire logic scheme for performing a division operation described in the conclusion shows that this operation is executable over the switching time of the combinational scheme. Thus, the calculation of the two results is as fast as possible, which can be achieved. A further exemplary logical structure of the divider with a micropipeline organization is also presented. It is suitable for serial execution of operation division. The functionality of the presented here hardware divider is illustrated by numerical examples.
Key Words: Operation Division, Integer Numbers, Quotient, Remainder, Algorithm, Logic Scheme
DOI: 10.31474/1996158820191288996
Tyanev, D.S., Petkova, Y.P. HARDWARE DIVIDER. CALCULATION OF THE REMAINDER CompSysTech '19 Proceedings of the 20th International Conference on Computer Systems and Technologies Pages 3135. ACM New York, NY, USA ©2019, ISBN: 9781450371490, doi:10.1145/3345252.3345266.
Theoretical basis and the resulting algorithm for calculating the remainder of 2's complement signed numbers integer division operation is presented. A logic scheme for calculating the remainder according to the nonrestoring division algorithm is synthesized. A structural scheme for micropipeline organization of the computations is presented. The logic scheme, along with that for computation of the quotient for the same operation (synthesized and published earlier by us [7]), makes a division operation executable over time to switch the entire combinational scheme. Thus, the calculation of the two results from operation division by this logical scheme is as fast as possible, which can be achieved. The functionality of the scheme is illustrated by numerical examples.
Tyanev, D.S., Petkova, Y.P. HARDWARE DIVIDER Proceeding of the International Conference CompSysTech’18, Ruse, Bulgaria, September 1314, 2018. pages 139143. ACM: New York, USA, ISBN: 97814564256. doi: 10.1145/3274005.3274009.
Operation division is the slowest of the four basic arithmetic operations performed in arithmeticlogic devices. In this paper we offer a proposal to speed up computations based on nonrestoring division algorithm by the use of the radix2 two's complement signed numbers. Fast computation is achieved by the early termination of the algorithm when the relevant condition is in place. A hardware implementation of the solution is proposed.
http://dl.acm.org/citation.cfm?id=3274009 Dimitar Tyanev, Yulka Petkova HANDSHAKE CONTROLLER FOR 3ALTERNATIVE CONDITIONAL TRANSITION 17th International Conference on Computer Systems and Technologies, 2324 June 2016, Palermo, Italy. Proceedings of CompSysTech'16, ISBN: 9781450341820, pages 159166. doi:10.1145/2983468.2983503.
The logical synthesis of an asynchronous micropipeline controller for a micropipeline unit with conditional algorithmic branch is presented. The condition for branch is generated by the operation comparison. The comparison by a digital comparator enables the realization of a unique 3alternative conditional branch. Such a branch can’t be software implemented. Only the hardware realization of the operation comparison generates such a unique conditional transition. The synthesized logical circuits of the logical units in the structure of the micropipeline controller are presented. The digital comparator as a part of the micropipeline unit generates transition flags LT, EQ and GT, defining each of the conditional transitions only into direction “true” (logical “1”). It is shown that the implementation of other conditions for a transition is basically possible by additional hardware resources that do not change the concept of the pipeline controller. The synthesized pipeline controller implements 2phase transfer protocol. Key words: Asynchronous MicroPipeline, Nonlinear Pipeline, Celement, Pipeline Controller.
http://dl.acm.org/citation.cfm?id=2983503&CFID=697072631&CFTOKEN=36879544 Dimitar Tyanev, Yulka Petkova EARLYZERO 4PHASE MICROPIPELINE CONTROLLER WITH PROTECTION 16th International Conference on Computer Systems and Technologies, 2526 June 2015, Dublin, Ireland. Proceedings of CompSysTech'15, ISBN: 9781450333573, pages 260267. doi: 10.1145/2812428.2812452.
A thorough and detailed analysis of anasynchronous 4phase transfer protocol with earlyzero reset is presented. The protocol is implemented by a micropipeline controller whose registerfixative (pipeline register) is implemented by dynamic (Edge) flipflops, writing data by the rising edge of the signal. Based on this analysis two original results are obtained. The first one: the possible time interval for the reset of the micropipeline controller is defined. The second one is about the possibility of false switching of the controller. Different variants of logic schemes are commented in relations with the findings of the analysis. Technical requirements which the logical synthesis is based on are defined for both problems. The principle logical circuit of the pipeline controller is presented. It’s functioning is explained in details by a timing diagram.
http://dl.acm.org/citation.cfm?id=2812428.2812452&coll=DL&dl=GUIDE Dimitar S. Tyanev COMPLETION DETECTION MODEL FOR A DIGITAL COMPARATOR SciTechnol: Journal of Computer Engineering & Information Technology, USA, ISSN: 23249307, 2015, Vol. 4, Issue 1. doi: 10.4172/23249307.1000124
The process of switching in a multibit magnitude comparator has been analyzed as well as the latency with which the output features are formed. A critical analysis of the possible methods for logic gate latency evaluation is presented, namely dualrail signal disjunction, Muller Celement and NULL Convention Logic (NCL). A new economical logic circuit for realization of completion detection when performing the operation comparison has been proposed in connection with the conclusions made. The synthesized logic circuit is based on the parallelism in the comparator circuit. The signal generated by the aforementioned circuit enables the comparator to function under the conditions of asynchronous control.
http://www.scitechnol.com/completiondetectionmodelforadigitalcomparatorvt7j.php?article_id=3260 Dimitar S. Tyanev, Yulka P. Petkova LOGIC SCHEME FOR DETERMINING THE NUMBER OF LEFTMOST INSIGNIFICANT DIGITS IN A BITSET OF ANY LENGTH SciTechnol: Journal of Computer Engineering & Information Technology, USA, ISSN: 23249307, 2015, Vol. 4, Issue 1. doi: 10.4172/23249307.1000123
The synthesized logic scheme is capable of determining the number of the leftmost insignificant digits of numbers, which are presented in a bitset of any length. The content of the bitset can be interpreted in different ways – as signed magnitude, one’s complement or two’s complement number and also as fractional binary number. This allows the scheme to be used in devices working both with fixedpoint and floating point. The number of leftmost insignificant digits of the number is necessary to implement the next highly productive oneclock left shift. This microoperation has place in the algorithms of various machine operations performed in the digital processor. The suggested scheme does not depend on the length of the bitset because of the cascade principle applied. The synthesized building unit solves the same problem and has a minimum length of 3 bits.
http://www.scitechnol.com/logicschemefordeterminingthenumberofleftmostinsignificantdigitsinabitsetofanylengthhRjK.php?article_id=3259 Dimitar S. Tyanev, Dimitar G. Genov MULTIFORM, MULTIFORMAT DIGITAL COMPARATOR SciTechnol: Journal of Computer Engineering & Information Technology, USA, ISSN: 23249307, 2014, Vol. 3, Issue 1. doi:10.4172/23249307.1000117
In this paper we analytically prove the possibility for synthesis of multiform, multiformat digital comparator based on the unsigned comparison algorithm of binary numbers. The synthesized comparator is a new unique logical circuit, which is capable of comparing signed binary integers and binary fractions as well as binarycoded decimal numbers. This circuit is also capable of comparing floatingpoint numbers as represented in the IEEE754 standard. The comparator is highly applicable since it integrates many different ways of representing the compared numbers by using this algorithm. It can successfully replace the traditional algorithm for comparison based on subtraction, which is used in digital processors. The comparator latency has been explored because it is necessary when the comparator is used in asynchronous control systems. The law of the latency distribution and its parameters have been defined.
http://scitechnol.com/multiformmultiformatdigitalcomparatorTlBS.php?article_id=1979 Tyanev, D. S. BCDADDER IN A WEIGHT CODE 5211 Computer Science and Technologies, ISSN 13123335, ¹ 3  2014, pp. 0105.
The structure synthesis of binary coded decimal adder in a weighted code 5211 is presented. This code is a question of present interest because of the developing of the hardware implemented decimal arithmetic, which basic goal is to avoid the known problems of the binary. The synthesis is presented in two versions for two of the 64 code tables. Both addition and subtraction operations are considered for each code table. Two logical structures for addition and subtraction of integers represented in complementary code are synthesized. Numerical examples are described. They illustrate the formulated rules and the functioning of logical structures for each of the code tables.
Tyanev, D. S. ASYNCHRONOUS MICROPIPELINE LOOPSTRUCTURES WITH MULTISTAGES BODY’S Computer Science and Technologies, ISSN 13123335,
A new method for hardware realization of algorithmic loopstructures with asynchronous micropipeline organization is represented. The study was on a loops with postcondition and body’s with common structures. For loops with beforehand unknown number of repetitions, presented pipeline organization is only possible. Four new tasks for pipeline organization are formulated and solved. The synthesis and logical circuit of the necessary pipeline controllers are representative.
Tyanev, D. S. SERIAL EARLYZERO 4PHASE MICROPIPELINE CONTROLLERS Computer Science and Technologies, ISSN 13123335, ¹ 3  2014, pp. 0517.
Analysis of the 4phase transfer protocol is presented. Conclusions are made and are defined technical requirements to parameters that are base of the logical synthesis. Principal logical schemes of serial 4phase pipeline controllers and additional circuits are presented. The functioning of these schemes is presented as well. Their advantages and disadvantages are defined which is a precondition fro their usage.
Tyanev, D. S. ASYNCHRONOUS MICROPIPELINE UNIT WHIT DIGITAL COMPARATOR Computer Science and Technologies, ISSN 13123335, Year XI, No 1 / 2013.
The process of switching a circuit of a digital comparator is analyzed. Based on the derived conclusions logic circuit is proposed for the realization of a new and original practical model of the completion detection in the execution of operation comparison. The signal generated by the synthesized circuit allows the asynchronous control method of the micropipeline unit.
Dimitar Tyanev, Antoniya Tyaneva PERFORMANCE ESTIMATION OF MICROPIPELINE BASED CALCULATIONS Applied Technologies and Innovations, Volume 7, Issue 2, June 2012, Prague Development Center, Czech Republic, ISSN: 18041191, pp. 7781.
Main focus of this article is the performance estimation of any arbitrary computational structure in various forms of control organization. Four organization cases are observed – sequential processing of high number of tasks by classical control of the computing structure using (synchronous and asynchronous) end state machine and parallel processing of tasks, organized in pipelined computational structure (synchronous and asynchronous controlled). The latency of each operational level is approximated with normally distributed random variable.
Dimitar Tyanev SUPERSCALAR MICROPIPELINE STRUCTURE Applied Technologies and Innovations, Volume 6, Issue 1, March 2012, Prague Development Center, Czech Republic, ISSN: 18041191, pp. 0109.
High latency micropipeline stage problem is analyzed. It is shown that in order to achieve steady pace into pipeline is necessary to apply superscalar approach. The formula for machine duplication degree is defined. The problems derived from this type of machine parallelism are stated. Synthesis of the micropipeline automat at the branch dot is presented in two variants – for 2phase and 4phase transfer protocol.
Tyanev D.S., Popova S.I. BRANCH MANAGEMENT INTO MICROPIPELINE JOINT DOT Applied Technologies and Innovations, Volume 5, November 2011, Prague Development Center, Czech Republic, ISSN: 18041191, pp. 1126.
This paper considers problems related to hardware implementation of computational process with conditional jumps. Hardware refers to asynchronous pipeline organization at microoperational level. Exploration is dedicated to one of the tasks presented in (Tyanev, D., 2009) concerning to micropipeline controller design to control micropipeline stage into joint dot of branch algorithm. Joint dot is the point at which few preceding branches are combined. It appears inevitably into conditional jump structures and this is the reason for the actuality of its problem. Analysis of this new task is presented and request arbitration functioning principles are formulated for the incoming to joint dot requests. The arbiter is responsible for the fair choice on which depends steady peformance of separate pipeline brances. Paper also describes pipeline controller synthesis and analysis of its operation in two variants: about 2phase and 4phase data transfer protocol. The synthesized asynchronous arbiter scheme is invariant to the type of pipeline protocol.
Tyanev D.S., Yanev D.V. NONLINEAR ASYNCHRONOUS MICROPIPELINES International Conference on Computer Systems and Technologies, (CompSysTech’11), Vienna, Austria, 1617 June, ACM ISBN: 9781450309172, ACM Press, pp. 3844, 2011.
The paper considers structural problems in synthesis of micropipelines which implement algorithms with conditional jumps. These structures require predefinition of the term "micropipeline". As a result there are defined, analyzed and described four new scientific tasks necessary for solving this common problem. The paper presents the solution of only one of the tasks  synthesis of micropipeline that controls section generating value of the transition condition, as well as the connection of this section with initial stage controllers into both branches. The complete logical synthesis is explained and as a result logical structures of pipeline controllers are obtained in two variants: for 2phase data transfer protocol and for 4phase data transfer protocol.
Tyanev D.S., Bojikova V.T., Gerganov S., Georgiev B. ALGORITHM FOR MICROPIPELINE BUFFER CONTROL Applied Technologies and Innovations (ATI), Volume 4, April 2011, Prague Development Center, Czech Republic, ISSN: 18041191, pp. 1221.
The paper focuses on the problem of hardware implementation of computational process containing conditional transitions. Asynchronous organization of pipelines at microoperational level is provided for the hardware. Its characteristic feature is that it includes both one and multicycle micropipeline units. Because of these circumstances, the outgoing pipeline results do not correspond in the same order to the tasks running in the pipeline. The article presents the synthesized original logical structure of the micropipeline buffer and a specific to its service strategy through which their correct order is restored when reading results from the buffer. Another programming model of the structure of the buffer is described, by which its behavior was studied in different possible situations. In addition, a programming model of the structure of the buffer was created and its behavior in different possible situations is examined. The results of numerical experiments with the programming model are presented. Based on them recommendations are formulated about the parameters of the buffer and the structure of the pipeline.
Tyanev D.S., Kolev S.I., Yanev D.V. RACE CONDITION FREE ASYNCHRONOUS MICROPIPELINE UNITS International Conference on Computer Systems and Technologies  CompSysTech’10, 1718 June 2010, Sofia, Bulgaria. ACM ISBN: 9781450302432, ACM Press, pp. 3137, 2010.
A new design is presented, which manages the problem with the internal race conditions in two types of micropipeline units (stages), which on their turn are hardware implementations of countcontrolled loops. The, implemented in the new design synchronization, eliminates the typical for the structures limitations and makes their operability fully synchronous and highly reliable.
Kolev S.I., Tyanev D.S. EARLY SET TO ZERO MICROPIPELINE International Conference on Computer Systems and Technologies  CompSysTech’10, 1718 June 2010, Sofia, Bulgaria. ACM ISBN: 9781450302432, ACM Press, pp. 2530, 2010.
A micropipeline, which consists of onecycle and multicycle micropipeline units, is considered. Along with the purpose to design unified and independent of the micropipeline unit structure control circuit, a unified interpretation of the pipeline organization is proposed. This interpretation sets to foreground the write to pipeline register microoperation. The implementation of a pipeline according to that interpretation is limited by the type of the registers, used to store the pipeline stage data, which are registers using only one edge (rising or falling). The mentioned limitation necessitates the usage of fourphase pipeline unit communication protocols. Accordingly, an asynchronous micropipeline and its control are designed. The control is capable of combining the two types of micropipeline units. The operation of the protocol is shown.
Tyanev, D. S., Petkova, Y. P. ASYNCHRONOUS MICROPIPELINE WITH MULTISTAGE SECTIONS ICEST'2010 pp.3841  XLV International Scientific Conference on Information, Communication and Energy Systems and Technologies. University "St. Clement Ohridski“, Ohrid, Macedonia. 2326 June 2010.
The interface of multistage micropipeline sections building continuous micropipelines is defined and analyzed. As the multistage micropipeline sections have own memory, such micropipelines don’t need additional registers. In these conditions there is pipeline asynchronous protocol and implementing control unit synthesized. The protocol’s operation is shown in cases, arising from combined work of neighbor multistage micropipeline sections. Possible problems of combining one and multistage sections are indicated.
Tyanev D. S., Kolev S. I. PRINCIPLE SCHEME OF APERIODIC FINITE STATE MACHINE Computer Science and Technologies, ISSN 13123335, ¹2 / 2008, pp. 38.
In the present work, an original logic structure of control unit based on finite state machine, with hardwired rules (FSMHRCU), working with floating cycles duration is presented. The structure may be used as basis for the implementation of either Mealy or Moore finite state machine. The operation of the synthesized structure is clarified schematically and graphically. The possibility of the execution of nano and picoprograms in the terms of the current microcommand from the sequence of microcommands of the controlling algorithm, is presented. The structure supplies aperiodicity in these low levels and it is synthesized and presented below in the paper.
Dimitar Tyanev, Dragomir Yanev, Stamen Kolev METHOD FOR REALIZATION OF SELFCONTROLLING LOOP APPARATUS STRUCTURES Fifth International Conference Computer Science'09 , 0506 November 2009, Sofia, Bulgaria
This paper presents a novel methodology for design of operational computational devices, realizing a diversity of conditioncontrolled loop algorithmic structures. The synthesis of such a structure takes in count just the necessary for the computation signal changes, which makes the synthesis of controlling finite state machine unnecessary. Thus the resulting controlling circuit is tightly coupled with the logic one. In this sense the structure can be defined as selfcontrolling and can be part of micropipeline structure with certain delay. The structures in either case are as fast as possible. Experiments have been made with Xilinx’ FPGA chip.
Dimitar Tyanev, Stamen Kolev, Dragomir Yanev MICROPIPELINE SECTION FOR CONDITIONCONTROLLED LOOP International Conference on Computer Systems and Technologies  CompSysTech’09. 1819 June 2009, University of Ruse, Bulgaria
This paper presents a novel methodology for design of operational computational devices, realizing a diversity of conditioncontrolled loop algorithmic structures. The synthesis of such a structure takes in count just the necessary for the computation signal changes, which makes the synthesis of controlling finite state machine unnecessary. Thus the resulting controlling circuit is tightly coupled with the logic one. In this sense the structure can be defined as selfcontrolling and can be part of micropipeline structure with certain delay. The methodology can be applied when designing either synchronous or asynchronous structures. The structures in either case are as fast as possible because they can be organized in pipeline fashion.
Stoyan Prokopov, Dimitar Tyanev HARDWARE IMPLEMENTATION OF STRATEGIES FOR SERVICING QUEUES International Conference on Computer Systems and Technologies  CompSysTech’09, 1819 June 2009, University of Ruse, Bulgaria
This article explores two original hardware solutions for service of queues. The threeclock cycle is proven as a necessity for a reliable choice process. Two logic structures are presented: oneclock and manyclock, each capable of servicing the two types of queues  with and without jumping. The algorithms representing the structures' functioning are thoroughly explained. The schemes allow a wide degree of adaptivity and can easily be integrated into projects, based on FPGA or CPLD, when constructing interrupt control systems, arbitrary systems, etc.
Dimitar Tyanev, Stamen Kolev, Dragomir Yanev METHOD FOR REALIZATION OF SELFCONTROLLING LOOP APPARATUS STRUCTURES  part II "Computer science & Technologies", TUVarna, ISSN 13123335, VI, ¹1/2008, p. 3135.
The present research represents a novel method for operational structures design, which implement a versatile set of countcontrolled loop algorithms. Main feature of these structures is that they operate without controlling automata. The method can be used for the design of synchronous and asynchronous structures. It simplifies the structures, gives us the ability to organize the structures in pipeline fashion, which results in better throughput.
Tyanev D.S., Nikolov N.N., Popova S.I. SYNTHESIS AND COMPARATIVE ANALYSIS OF MULTIPLE INPUTS PARALLEL ADDERS  part II Fourth International BulgarianGreek Conference – “Computer Science'2008”, 1819 September 2008, Kavala, Greece, Proceedings  Part I, p. 270278.
This article consider/explore simultaneously addition of more than two integer numbers problem through (3:1) concentrators. Presented results are extension of previously published research of the problem, solved about horizontal organized addition. In this paper we discuss second possible organization, referred as vertical addition. Logical structure, which implements such organization, has been synthesized and analyzed. The analysis, as well as obtained quantitative estimations of machine costs and switching time, is presented. Conclusions based on the comparison of the two structures were made. Recommendations for design of solutions with different parameters have been formulated. Particular examples have been molded and implemented experimentally through Xilinx tools.
Dimitar Tyanev, Stamen Kolev, Veselin Josifov METHOD FOR REALIZATION OF SELFCONTROLLING LOOP APPARATUS STRUCTURES Proceedings of TUVarna, 2007
The new approach was explored for hardware implementation of calculation procedure, the cardinal characteristic to which the rule of the synthesized procedure structures in the absence of microprogram control in the synthesized operational structures. The general method for the hardware execution is exposed in the present work on autonomous loop algorithmic structures. The operating capability to the represented structures is showed by modeling and practical experiment in real calculation drives on the base of the company Xilinx.
Veselin Josiffov, Stamen Kolev, Dimitar Tyanev OPERATIONAL STRUCTURES WITHOUT CONTROLLING AUTOMATA International Workshop on Network and GRID Infrastructures: http://bis21pp.acad.bg/events/iw_27280907.htm , 2728 Sept 2007, Bulgarian Academy of Sciences, Sofia, Bulgaria.
This document presents a new method for design of operational computational devices, in a way that a FSM is removed from the design. The method can be used for the design of synchronous and asynchronous devices. The main advantages of the method are the simplification and homogenization of the devices and as well the opportunity of increasing the output of the computational devices.
Dimitar Tyanev, etc. CONVEYER MULTIPLIER WITH CONCENTRATORS "Computer science & Technologies", TUVarna, ISSN 13123335, IV, ¹2/2006, p. 2328.
This article consider/explore simultaneously addition of more than two integer numbers problem through (3:1) concentrators. Presented results are extension of previously published research of the problem, solved about horizontal organized addition. In this paper we discuss second possible organization, referred as vertical addition. Logical structure, which implements such organization, has been synthesized and analyzed. The analysis, as well as obtained quantitative estimations of machine costs and switching time, is presented. Conclusions based on the comparison of the two structures were made. Recommendations for design of solutions with different parameters have been formulated. Particular examples have been molded and implemented experimentally through Xilinx tools.
Tyanev D.S., Popova S.I., Ivanov A.I., Yanev D.V. SYNTHESIS AND COMPETITIVE ANALYSIS OF MULTIPLE INPUTS PARALLEL ADDERS  part I Ñïèñàíèå “Êîìïþòúðíè íàóêè è òåõíîëîãèè”, ÒÓÂàðíà, ISSN 13123334, ãîäèíà III, áðîé ¹2/2005, ñòð. 5161.
This paper submit the idea for parallel at time adding of more than two integer numbers with schemes, known as concentrators. A logic structure of adder with multiple inputs, based on threeinput adder, is offered. Theorem for the highest length of the sum is proved in conditions of arbitrary numbers. On the ground of this theorem there are analytical estimations of implementation costs and switching time. Comparative analysis of the competitive schemes is shown. The conclusions proof acceptability of both researched idea and offered scheme. The experiments with the schemes were made with the help of Xilinx tools and FPGAfamily Spartan II.
Petkova Y.P., Tyanev D.S. MATCHING CRITERIA IN TEMPLATE LOCALIZING – COMPARATIVE ANALYSIS OF EXPERIMENTAL RESULTS Âòîðè ìåæäóíàðîäåí íàó÷åí êîíãðåñ MEEMI’2005, Âàðíà, 78 Îêòîìâðè 2005.
In the present paper we made an analysis of different matching criteria, which are applied when a task of template matching is solving. It is made an analysis of the experimental results, which are derived when these different criteria are applied on the selected sets of representative points. Comparisons are made about two basic criteria – speed and how they cope with any type of distortions.
Petkova Y.P., Tyanev D.S. THRESHOLDING IN EDGE DETECTION Procesing of the International Scientific Conference “Computer Science’2005”, 30 sept. – 02 Okt. 2005, Possidi, Chalkidiki, Greece.
Many edge detectors are described in the literature about image processing, where the choice of input parameters are to be made by the users. In many cases such choices are made intuitively. In this paper we propose the choice of threshold to be based on the visual perception of the edge. Using our earlier edge definition and proposed algorithm for edge detection we formulate a minimax rule for threshold determination. This rule uses the values of the second derivative of intensity function. Choice of the most significant values of second derivative allows to separate areas, which contain edges. The proposed approach is applied in the developed by the authors edge detector. The derived results are satisfactory.
Tyanev D. S., Petkova Y. P. ABOUT THE POSSIBILITIES OF A NEW EDGE DEFINITION IN BLACK AND WHITE IMAGES 28th International Spring Seminar on Electronics Technology, ISSE 2005, 1922 May, Vienna, Austria, IEEE Catalog Number 05EX1142C, ISBN: 0780393252.
This research is devoted to the problems in the field of black and white image processing which are connected with the purpose to detect the maximum number of edges and to determine their coordinates as exactly as possible. It is made a critical analysis of the commonly accepted definition of the edge, modeled as a ramp. Consent to this definition there is only an edge, which position is in the middle of the ramp connecting low and high level of intensity. Here authors give a new edge definition; according to it there are two edges (contrary to the classical definition) – one on the low level and a second one – on the high level of intensity. As a result of this understanding, suggested here definition is mathematically formalized by the interrupted first derivative of the intensity function. Based on this definition authors work up an edge detector achieving subpixel accuracy when detects edge points’ coordinates. There are synthesized appropriate test images and some of the well known edge detectors and the here suggested one are applied to them. Results confirm authors’ expectations for accuracy of localization and high informativity in the description of the objects in black and white images, which comes very close to their visual susceptibility.
Tyanev D. S., Petkova Y. P. A NEW METHOD FOR IMPORTANT POINTS EXTRACTION Proceedings of the International Conference on Computer Systems and Technologies – ComSysTech’2004, Ruse, Bulgaria, 1719 June, 2004
Template matching is one of the most important problems in the vision industry. This problem is solving by many different ways, but along with the requirements of high reliability, there are high requirements of runtime decreasing. One of the ways to speedup the processing is to reduce the number of points (pixels) which take part in the calculations. We propose a new method for important point’s extraction, based on the equipotential surfaces. By the properly potential threshold these surfaces give a possibility to extract the elements of searched subset of points, which are in conformity with the criterion of Doptimality. The successful fulfillment of this extraction can be made by the properly conditions. For this purpose we propose a method for nonlinear interval transformation of the color function. This transformation leads to the image contrast improvement and thence to the more easily determination of the coordinates (x,y), corresponding to the intersected points of the relief with the surface of the properly chosen potential.
Tyanev, D., Petkova Y., Tyaneva A. NEW ELEMENTS IN THE METHOD OF MCLARENMARSAGLIA Sovidius University Annals of Mechanical Engineering, volume IV, Tom I, year 2002, CONFERENCE PROCEEDINGS of “TEHNONAV 2002”, p. 402404, Constanta, Romania, 30 May – 1 June 2002, ISSN 12237221. According to the analysis of the McLarenMarsaglia’s method for random sequences generation is established the possibility that the function which services the temporary buffer to be interpreted as a hashfunction. As a result of this conclusion a new function of multiplicative type is suggested. There are described the results of the modified algorithm compared to the original one, based on Kolmogorov’s criteria. Tyanev D. S. A NEW CRITERION FOR QUALITY ASSESSMENT OF COMPUTER GENERATORS OF RANDOM NUMBERS Íàóêîâi ïðàöi Äîíåöüêîãî Äåðæàâíîãî Òåõíi÷íîãî Óíiâåðñèòåòó, Äîíåöê, Óêðàèíà, 2000, Âèïóñê 15, ñòð. 6569. As a criterion for assessment of computer generators of random numbers with standard normal distribution, a limit is offered, corresponding to an estimated level of risk. A method for calculation of the criterion is being proposed, as well as the results of its application. Tyanev D. S. COMPUTER GENERATION OF RANDOM VECTORS WITH GUARANTEE OF THE STATISTICAL PARAMETERS USING THE MONTECARLO METHOD Íàó÷íà ñåñèÿ'98 ñ ìåæäóíàðîäíî ó÷àñòèå  "Ãîäèíà íà ñâåòîâíèÿ îêåàí" , 1314 Îêòîìâðè 1998, Âàðíà. The objects of comment in this paper are the deficiencies of computer generated standard normal statistical samples yielding to the N(0,I) law and the impossibility of the generators to guarantee the statistical parameters assigned in advance. An approach for appropriation of the statistical samples of a priori known mean vector and covariance matrix in absolute conformity with the N^{(k)}(v,Ñ) law is suggested. Tyanev D. S. ORGANIZATION OF DMATRANSFER FOR ISABASED A/D CONTROLLERS Proceedings of 11th International Conference "Systems for automation of engineering and research and DECUS NUG Seminar'97, St. Konstantin resort  Varna, Bulgaria, 2021 Sept. 1997, p. 5963. The object of discussion in this study are the foremost means for data input through the channels for direct memory access by ISAbased controllers, intended for synchronic and asynchronic analogdigital conversion. The requirements of the process of transfer needed for synthesis are also clarified. The potential technical and program solutions are based on two of the DMAcontroller operation modes  single transfer mode and block transfer mode. Tyanev D. S. RECOGNITION RULE FOR NORMALLY DISTRIBUTED VECTORS AFTER SECONDARY ORTHOGONAL TRANSFORMATIONS Proceedings of 11th International Conference "Systems for automation of engineering and research and DECUS NUG Seminar'97, St. Konstantin resort  Varna, Bulgaria, 2021 Sept. 1997, p. 117121. On the basis of a critical analysis of the orthogonal transformations used in the problems of pattern recognition, a new method of approach is suggested, which is meant for the optimization of the orthogonal feature spaces. This approach consists in accomplishment of consecutive secondary orthogonal transformations by manipulating the parametres of the eigen basis systems to the optimal point of view. The latter is determined by the use of the term secondary scalar feature. In connection with the introduced presentation of classes, a classification rule is formulated. Tyanev D. S., Dobrev P. D. TWO CHANEL 16 INPUTS A A/D CONTROLLER WITH DMA FOR IBM PC/AT Proceedings of 8th International Conference "Systems for automation of engineering and research" and DECUS NUG Seminar'94, St. Konstantin resort  Varna, Bulgaria, 12 Octob. 1994, p. 187194. This paper presents harware and software realization of ADCcontroller fot IBM compatible AT/PC; exchanging data via 16bits chanels, by DMA. ADC converts two input signals parallel in time. Two additional pulse imputs of the controller mark the current reports in thr two channels. This makes the system convinient for control and analysis of fast  going processes in rotational or reciprocating drive objects, which require link between monitored processes and certain one. The software for the controller consists of two parts  basic and applicable one. Rezults from real use the hardware in control and analysis of the combustion processes in diesel engines are also presented. Tyanev D.S., Atanasov A.N. REGARDING THE SELECTION OF OPTIMUM TEACHING STATISTICS FOR SOLVING PROBLEMS OF IDENTIFYING IMAGES 15th Session of Scientific Seminar on Ship Hydrodynamics, vol. 2  27/127/4, Varna, X.1986. The paper deals with the problem of forming teaching sample from the statistics accumulated for given class. The teaching sample should guarantee a qualitative teaching of the identifying algorithm, more over a sertain level of its efficiency is achieved at less volume of the same. For this purpose the criterion of Doptimum of the sample is applied in cojunction with the method for SVD when computing the determinants. As a result, procedure for forming sample of given volume is syntesized. Estimates of quality of the linear dividing funkction are made when teaching the so formed teaching sample. The results from the computing experiment with linear dividing function teached in different ways for solving concrete problem of ship's diesei engine diagnostics are shown. Kolev N.S., Uzunov G.K., Vlasakov V.L., Tyaneva Z.G., Tyanev D.S. INFLUENCE OF ACUTE HAEMODYNAMIC CHANGES ON THE POSITIVE PEAK OF THE FIRST DERIVATIVE OF THE APEX CARDIOGRAM OF DOGS Acta Medica Academica Scientiarum Hungaricae, Budapest, Tomus 38(4), p. 357363, 1981. The effect of various alterations in preload, afterload and inotropic state of the left ventricle on the derivative of the left apex cardiogram (dA/dt) was studied in anaesthezed dogs, in an attempt to clarify some of the determinants of the positive peak of dA/dt and time interval from the onset of ventricular contraction to the maximal dA/dt (tpeak dA/dt). The first derivative of the apex cardiogram was recorded simultaneously with left ventricular pressure, conventional left apex cardiogram, the first derivative of left ventricular pressure, electrocardiogram and phonocardiogram. Both dA/dt and dP/dt curves similar in contour and were found to occur nearly simultaneously. This close relation was preserved during various acute haemodynamic chages. Peak positive amplitude dA/dt was closely related to the myocardial inotropic background and to the pre and afterload. In addition, tpeak dA/dt was inversely dependent on the ventricular inotropic state and statistically nonsignificant changes on varying the loadeng condition. It is concluded that the combination of peak positive amplitude dA/dt and tpeak dA/dt allow a more precise and complete estimation of changes in contraetility than could be obtained from peak amplitude dP/dt used separately.
